FIG. 1 illustrates a high speed digital system 100 including a drive circuit 110 receiving a signal SIG and outputting a signal to receive circuit 130 via an existing connection circuit 120 and connectors C, such drive circuit 110 and receive circuit 130 being driven by a common clock signal CLK provided along a clock line 140. The components within the drive circuit 110 and receive circuit 130 (e.g., both which may be implemented via IC chips) are manufactured to have sub-micron dimensions and micron spacings between such components, and accordingly, signal propagation time from one internal IC element to another internal IC element is substantially negligible. As a result, the internal IC circuits operate at extremely high speeds, e.g., chips typically now operate with internal clock speeds in excess of 100 MHz. The present invention arises from the problem that external component spacings outside of the ICs (e.g., spacing between IC chips) are not matching the component spacings within ICs making it difficult if not impossible to manage synchronization with respect to downstream signals.
In a system, there may be physical limitations as to how closely spaced a drive circuit 110 and a receive circuit 130 can be placed. More specifically, in highly dense systems having a plurality of interconnected printed circuit boards (PCBs) with several tens/hundreds of IC chips, a tremendous number of interconnection lines, numerous connectors and several hundreds/thousands of supporting components (e.g., resistors, capacitors, inductors, etc.), a drive circuit 110 and a receive circuit 130 may need to be spaced at a substantial distance D (e.g., up to ten to fifteen inches) from one another. Resultant signal propagation along the substantial distance D, and especially through connectors C and any existing circuit 120 may cause a propagating signal not to meet a setup time of the receive circuit 130, i.e., cause a synchronization mismatch between the drive and receive circuits.
More specifically, assuming that the signal SIG is processed and output by drive circuit 110 at a time t=0 (FIG. 2) coincident with a first clock pulse 242 of a 100 MHz (i.e., megahertz) clock having 10 ns (i.e., nanoseconds) clock periods, and does not arrive at an input of receive circuit 130 until 13 ns later, such signal cannot be input into receive circuit 130 upon occurrence of the second clock pulse 244, i.e., it arrives too late at the receive circuit. As a further problem, it is unlikely that such output signal will remain prevalent (i.e., valid) at an input to receive circuit 130 for another 6–7 ns so as to be available for capturing by receive circuit 130 upon occurrence of a third clock pulse 246. Accordingly, a window of availability of the propagated output signal at the input of receive circuit 130 does not match a predetermined setup time window required by receive circuit 130.
In high-speed I/O designs, the timing specifications allow for very little variation. The timing allocation for each component comes from estimates that are susceptible to errors. These allocations are sometimes altered after the design is completed to remedy violations. As the designs become increasingly complex and the design process becomes shorter, it is important to add features that allow corrections after IC chips are connected whenever necessary. These capabilities permit the design to be tuned in the face of uncertainties due to aggressive process scaling as well as ever changing product specifications.
A first solution skews the on-board clock routing to the transmitter and receiver chips with respect to each other once the systematic timing offset is known. The advantage to this solution is that the routing skews are quite constant across manufacturing conditions, but this requires additional board re-designs that slows the design process. In a second solution, on-chip delay buffers are added or removed from the transmitter or receiver chips in the data path to shift the timings. The advantage to this approach is that it does not require board re-designs, but it consumes a lot of space (i.e., in all I/O pad cells). In addition, since the cost of compensating these buffers would be astronomical, these non-compensated buffers will suffer from process, voltage, and temperature (PVT) variations. The delay buffers can be placed into the common clock path to remedy the penalty area. Again, these non-compensated delay buffers suffer from PVT variations that help one timing component, such as 200 ps setup time margin gain, but costs another timing component dearly, such as 400 ps hold time margin loss.